Call for Participation - Thermal Interface Material Performance Characterization Methodology, Phase 1
As demand for high-performance computing and AI accelerators escalates, effective thermal management becomes critical in electronic packaging. A key component is the Thermal Interface Material (TIM), which minimizes thermal resistance between the silicon die and its cooling modules. Current industry practice relies on the ASTM D5470 standard, which uses a heater-based setup to measure thermal resistance under steady-state, one-dimensional heat flow. While standardized and repeatable, this method does not replicate the complex thermal environment of real silicon devices. To address these limitations, this project proposes a more realistic and representative approach using the JEDEC JESD51-14 standard with a Thermal Test Chip (TTC) or Thermal Test Vehicle (TTV). This webinar will explain the motivation and scope with task plan will be explained to seek for the participants to the project.
Background
As high-performance computing and AI accelerators drive systems to unprecedented power levels, effective thermal management is critical in electronic packaging. Thermal interface material (TIM) is a key component for minimizing thermal resistance between the silicon die and its cooling modules, and an accurate TIM characterization is essential for reliable thermal performance. Join us to learn about the motivation for INEMI's Thermal Interface Material Performance Characterization Methodology Project and discuss project scope and Phase 1 tasks.
What You’ll Learn
- How current industry practice for TIM characterization does not accurately replicate the complex thermal environment of real silicon devices. It fails to simulate dynamic power profiles, non-uniform heating, complex interfacial thermal behaviors, and packaging-induced mechanical constraints, all of which can influence TIM performance in actual systems.
- How the JEDEC JESD51-14 standard can be used as the basis for a better approach to thermal management that includes spatially varying power densities and temperature gradients.
- How embedded sensors can enable high-resolution temperature mapping for accurate localized thermal characterization and improved thermal model validation.
Purpose of Project
This project will propose a more realistic and representative approach to thermal management based on JEDEC51-14 and will further expand the standard’s recommendations by:
- Developing measurement guidelines and test vehicles for high-power package thermal characterization.
- Defining a standardized fixture/cold plate design and packaging configuration to enable a fair comparison of TIM performance across the industry.
- Enhancing thermal model validation and simulation.
Project Leaders
- Dongkai Shangguan (Indium)
- Foo Siang Hooi (Indium)
- Chun Keang Ooi (Intel)
- Yvonne Yeo (IBM)
Who Should Attend
- OEMs, EMS companies
- Materials manufacturers
- Measurement equipment suppliers
- IC vendors and assembly houses
- Academic and research institution laboratories
Registration
This webinar is open to industry; advance registration is required. You will need to log into your web account (free to members and non-members) to register. If you do not have a current web account, please create one and set up your profile. If you have any questions or need additional information, please contact Masahiro Tsuriya ([email protected]).
Thursday, April 2 / 10:00-11:00 p.m. EDT (US)
Friday, April 3 / 11:00 a.m. – 12:00 p.m. JST (Japan)
Registration
Registration is closed.