Juan Landeros (Intel) talked about the impact of increasing bus speed on materials, design and architecture. On the materials side, improvements are needed in glass type, resin, oxide treatment, zero roughness copper and looking beyond copper. On the manufacturing side, there need to be improvements to back drill quality in terms of registration, stub length and exposed copper. Sarah Czaplewski (IBM) continued that discussion, noting that the push for faster data rates and more I/O is challenging for PCB fabrication methods. She discussed the issues with high aspect ratio plated through holes (≥ 20:1), especially in low loss materials, and recommended that more emphasis needs to be placed on optimizing PTH manufacturing process earlier in the product development cycle. She identified other challenges being faced such as ensuring microvia pad cleanliness, improved layer-to-layer registration for densely routed packaging, and the need for smaller antipads on backdrill layers to reduce z-axis crosstalk.