Inspection and Reliability Study of Voids in First-Level Interconnects for Flip Chip Packages

INEMI's 1st Level Interconnect Void Characterization project is studying the effect of voiding in first-level micro-bumps on the joint reliability and will develop guidelines regarding what type of voiding may be acceptable in certain applications. 

The evolution of electronic packaging to enable 3D heterogeneous integration has led to a continuous downscaling of solder interconnects. With the emergence of packaging technologies like silicon bridges, interposers and die-to-die stacking, micro-bumps in electronic packages are getting smaller and smaller. The shrinkage of bump size to cater to higher I/Os in increasingly complex packaging design can potentially lead to weaker interconnect joints. Common defects that are evident in larger solder joints could become critical in smaller micro-bumps.  One such defect is voiding. The presence of voids in small micro-bumps not only reduces solder volume and affects joint structural integrity but also restricts current flow and increases current density in the joint. Voids within flip chips also tend to grow, especially after multiple reflows. This can be a concern for certain applications that involve high electrical and thermal flux across the flip chip. Void formation can also impact electromigration in the joint which can accelerate failure. 

The aim of INEMI's ongoing 1st Level Interconnect Void Characterization project is to study the effect of voiding in first-level micro-bumps on the joint reliability and develop guidelines regarding what type of voiding may be acceptable in certain applications. Presently, there are no industry guidelines or standards that address how voiding affects joint reliability or specifies an acceptable level of voiding. This project has two distinct phases. The first phase includes an evaluation of the capabilities of existing X-ray equipment to identify and quantify micro voids, as well as developing a process for assembling test vehicles for testing. The second phase will study the impact of such voids on electrical and mechanical reliability of the joints. This article reports on the first phase and presents a summary of how the assembly process for suitable test vehicles with relevant voiding was developed and how the test vehicles were inspected.  

Test Samples Build 

Two different test packages were built for the assessment of different aspects of reliability. Figure 1 shows the two test packages with their respective bump layout. One will be used for electromigration testing and the other for thermal cycle and thermal shock testing. The detailed geometric dimensions for the two test packages are listed in Table 1. #SAC305 was chosen as the solder alloy for the first-level interconnects. Known key factors that can affect void formation in solder joints, such as the type of solder paste, flux, and reflow profile, were taken into consideration when developing the process recipes. To characterize interconnect voids, different materials and process setups were assessed with the intention of defining two distinct process recipes — one generating very little to no voiding and another that generates a lot of voids. Various process steps were assessed when building the test samples. Both solder balls and solder pastes were used as methods of depositing solder for the joints. Table 2 shows the experimental matrix for optimizing the assembly processes for the test packages. 

Various types of test samples were built in the first phase of this project. The first one was built by depositing solder balls on a substrate followed by a reflow process to form the joints. The second sample was built by printing solder paste on a substrate and then reflowing to form the joints. Flip chip test samples were also built by using dummy silicon. The first type of flip chip sample was built by attaching a silicon die on a pre-soldered substrate with a second reflow process. The second type of flip chip sample was built with a single stage reflow by directly attaching the silicon die right after the solder paste print process.

Void Inspection Results

X-ray is the preferred method of inspecting for voids. However, it is challenging to accurately locate and measure the size of the void or the percentage of voiding due to the small dimension of the flip chip bond and the interference of substrate and die metallization. Two different imaging techniques were used for void inspection in this work. The first was a conventional through-plane X-ray that can show the distribution of solder voids across a horizontal plane, capable of inspecting voids down to 0.1 um. The second was a more advanced CT scan with a resolution of 0.1 um that can provide oblique views of the solder joints. The CT scan was used to capture near-vertical slice images of the solder joints. The combination of both conventional X-ray and CT scan was able to adequately determine the size, position, and distribution of voids in the solder joints. 
 
Based on the X-ray images, a few observations can be made. Very few or close to no voids were observed in samples built with solder balls and flux paste. However, many voids were observed in samples built with solder paste. The variation in the type of solder pastes, fluxes and reflow profiles did not have a significant impact on the generation of voids. With the process flows shown above, voids tended to stay close to the substrate pads. The presence of a flip chip did not significantly alter the distribution of voids other than to cause some minor bump flattening and limited merging of adjacent voids. 

Summary

Test samples built with solder paste can generate adequate voids in most of the first-level micro bumps whereas test samples built with solder balls have very few or close to no voids. This capability of ensuring voiding and non-voiding enables the further experimentation that is planned. Void inspection using a combination of X-ray and CT has been seen to adequately determine the size and location of macro and micro voids in first-level interconnects. This information is important in the next phase of the experimentation where the impact of the size and location of the voids on joint reliability will be investigated. 

Further details about the experimental builds are available in this webinar presentation from February 2021.

Ongoing Work 

The work done in Phase 1 of the project defined the process recipes that will make it possible to consistently build test samples with and without first-level interconnect voids. Phase 2 of the project will focus on assessing first-level joint reliability in electromigration, thermal cycle and thermal shock testing. For additional information, contact Masahiro Tsuriya ([email protected]).