SOW & Project Statement
Statement of Work (v1.1, December 13, 2022)
Project Statement (v1.1, December 13, 2022)
Background
High density interconnect sockets are becoming larger due to the increased pin counts in flip chip land grid array (FCLGA) products such as CPUs and GPUs. This larger size causes challenges for socket warpage simulation and can impact SMT assembly yield and reliability. Simulation is critical in the product development process, helping manufacturers the right design choices before making significant investments in tooling and industrialization.
Socket warpage prediction is now facing a few challenges. The majority of simulation computation is consumed by flow analysis in the pin hole region. Expedited computation that maintains the required level of accuracy is needed to shorten socket design cycles.
In the 1st phase of the High Density Interconnect Socket Warpage Prediction and Characterization project, the team established an analysis and validation framework for socket development, conducted simulation experiments and compared with CPU socket samples, and initially investigated the impact of socket design, fiber filled material properties and molding process conditions to socket warpage. Results show computational time can be reduced for the flow part of simulation with reasonable accuracy.
Phase 2 will continue the work of improving socket warpage simulation accuracy and speed, further investigating the impact of molding and design on socket warpage, and ultimately establishing guidelines for dynamic socket warpage measurement and prediction.
Presentations
Presentation from end-of-project webinar (December 5/6, 2024)
Presentation from call-for-participation webinar (January 5/6, 2023)
"High Density Interconnect Socket Warpage Prediction and Characterization," Renn Chan Ooi (Intel Corp, Malaysia), Electronics Packaging Technology Conference (EPTC), December 9, 2022; Singapore) (members only; requires log-in) paper presentation poster
Contact
Haley Fu
[email protected]